This is in sharp contrast to simply being a Raven Ridge refresh on the same node with more optimized architecture and better binning. ‘The next five years are going to be fun’, Sam said.AMD also highlighted its work with TSMC on 7nm, with Sam stating that without it, achieving the goal would not have been possible. He pointed to the tribal knowledge of driving x86 at high-performance and at scale – although he did concede that Arm’s partners have a number of impressive core and SoC designs, and they are keeping tabs on what that market is doing. - Support MAX Height ≦ … Picasso APUs just became their very own line of products if this is actually the case.One thing is clear though, the 2018 time frame is probably a best-case scenario. Sam told me that based on those original targets back in 2014/2015, AMD exceeded his projects in CPU by some considerable margin, which offset some of the GPU projections.The PT(x) options are the power consumed in those modes. Here’s the important graph:And here are the raw results, with the key columns highlighted:As an aside, I did want to get Sam’s thoughts on how AMD is approaching the increasing competition from Arm based designs.
It is likely that AMD’s reference design mirrors this unit a lot, as AMD and HP work very close together. AMD took some time to reconfirm the correct numbers, and admitted that in light of some of the issues I’d found, previous data may have been incorrect as well (at one point they had moved a data point from a 19W CPU to a 35W CPU, among other issues).For anyone wondering, the equation for the ‘goal’ line approximates to:In speaking with AMD’s Sam Naffziger, he mentioned that when this project started, the company had created what it assumed would be the year-on-year targets for both the CPU and the GPU. Because the 'efficiency' part of the calculation is heavliy weighted towards idle, decreasing the latency for a CPU to enter and exit a turbo mode helps a machine power to idle quicker. With this year being 2020, the question on my lips ever since the launch of Zen2 for mobile was if AMD had achieved its goal, and if so, by how much?
On top of the core work, Arm’s partners still have the ISA/software porting task, and architecture transitions have to enable significant benefits and lots of investment to be taken advantage of. That you should take this with a grain of salt goes without saying.As is usually the case with such large processors, there will be smaller versions of the same (yield theory dictates that) and according to the source the TDP should vary between 35W and 180W for the entire range of servers. But clearly room for some improvement.Using Kaveri as a base result of 1.0, Carrizo scores 1.23, Bristol Ridge scores 1.36, and Raven Ridge 2017 scored 2.47 etc.With that being said, here are all the platforms that AMD has used for the 25x20 goal:In this article we will recap the 25x20 project, how the metrics are calculated, and what this means for AMD in the long term.The announcement today from AMD confirms the company has reached its goal of 25x performance efficiency by the end of 2020, starting from the Kaveri baseline. Even then, late 2018 is the earliest we can expect any working x86 processor on the 7nm node to materialize, otherwise, we are looking at the same 2019 estimates for 7nm chips.AMD Starship, on the other hand, is also based on the 7nm process and Zen2 architecture and will be a server CPU to go against Intel's Xeon Phi series. Raven Ridge is actually expected to debut in notebooks closer to the holiday season this year. This gives three distinct jumps:The jump from Picasso to Renoir is 2.92x, taking AMD to 31.77x over the original target. That’s in the fine print.For this disclosure, AMD has given us all the data as collected. Picasso is codename for AMD series of mainstream mobile and desktop APUs based on the Zen+ CPU and Vega GPU microarchitectures succeeding Raven Ridge. The main thing to bring up about this metric is that it ends up being highly dependent on the device or laptop the processor is being used in.
This boosted up the important 25x20 metric and keeping it well above the ‘linear’ gain.How did AMD define how the target will be measured? - Picasso, Raven Ridge, Bristol Ridge, up to 65W. At the time AMD was defining its Kaveri mobile product as the baseline for the challenge – admittedly a very low bar – however each year AMD has updated us on its progress. As the process node is shrinking in size - it is getting harder and harder to beat physics.
While GPU acceleration has made it into some aspects of a standard laptop-style device, it perhaps isn’t as ubiquitous as was originally envisioned, however the ultimate end-point ended up being a distinct CPU and GPU gain anyway. Picasso processors are fabricated on GlobalFoundries 12 nm process and incorporate four cores . Raven Ridge.
The best environment becomes this odd hybrid of premium components but low specifications.One of the stories bubbling away in the background of the industry is the AMD self-imposed ‘25x20’ goal.
The Xeon Phi co-processors will be the only offerings from Intel which will outstrip Starship in terms of the raw core count.